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LFXP25E7IQN208I Scheda tecnica(PDF) 23 Page - Lattice Semiconductor |
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LFXP25E7IQN208I Scheda tecnica(HTML) 23 Page - Lattice Semiconductor |
23 / 92 page 2-20 Architecture Lattice Semiconductor LatticeXP2 Family Data Sheet • In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. • In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle. • The loading of operands can switch between parallel and serial operations. MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-20 shows the MULT sysDSP element. Figure 2-20. MULT sysDSP Element Multiplier x n m m n m n m n n m m+n m+n (default) CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Pipeline Register Input Register Multiplier Multiplicand Signed A Shift Register A In Shift Register B In Shift Register A Out Shift Register B Out Output Input Data Register A Input Data Register B To Multiplier Input Register Signed B To Multiplier |
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