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LFSC3GA80KLUTSEP1F256C Scheda tecnica(PDF) 6 Page - Lattice Semiconductor |
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LFSC3GA80KLUTSEP1F256C Scheda tecnica(HTML) 6 Page - Lattice Semiconductor |
6 / 237 page 2-2 Architecture Lattice Semiconductor LatticeSC/M Family Data Sheet Figure 2-1. Simplified Block Diagram (Top Level) Programmable Function Unit (PFU) sysMEM Embedded Block RAM (EBR) Structured ASIC Block (MACO) Quad SERDES Physical Coding Sublayer (PCS) Quad SERDES Programmable I/O Cell (PIC) includes PURESPEED I/O Interface sysCLOCK Analog PLLs sysCLOCK DLLs sysCLOCK Analog PLLs sysCLOCK DLLs Each PIC contains four Programmable I/Os (PIO) Three PICs per four PFUs |
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