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M27W201-120NZ6TR Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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M27W201-120NZ6TR Scheda tecnica(HTML) 10 Page - STMicroelectronics |
10 / 24 page Device Description M27W201 10/24 2.6 Presto II programming algorithm Presto II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 26.5 seconds. Programming with Presto II consists of applying a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 5). During programming and verify operation, a Margin mode circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in Margin mode at VCC much higher than 3.6V, provides the necessary margin to each programmed cell. Figure 5. Programming flowchart 2.7 Program Inhibit Programming of multiple M27W201s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27W201 may be common. A TTL low level pulse applied to a M27W201's P input, with E low and VPP at 12.75V, will program that M27W201. A high level E input inhibits the other M27W201s from being programmed. 2.8 Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. AI00715D n = 0 Last Addr VERIFY P = 100 µs Pulse ++n = 25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES 1st: VCC = 5V 2nd: VCC = 2.7V YES NO YES NO YES NO |
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