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LD39150PU18R Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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LD39150PU18R Scheda tecnica(HTML) 5 Page - STMicroelectronics |
5 / 19 page LD39150 Typical application circuits 5/19 3 Typical application circuits (CI and CO Capacitors must be placed as close as possible to the IC pins) 1 Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device when connected to GND or to a positive voltage less than 0.3V 2 Set R2 as close as possible to 4.7K Ω. Figure 3. LD39150 fixed version with inhibit Figure 4. LD39150 adjustable version VO = VREF (1 + R1/R2) |
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