74LVX174 datasheet(4/12 Pages) STMICROELECTRONICS

Il numero della parte	74LVX174

Spiegazioni elettronici	LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR WITH 5V TOLERANT INPUTS

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74LVX174

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Table 7: Dynamic Switching Characteristics

1) Worst case package.

2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold

(VIHD), f=1MHz.

Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-

ing in the same direction, either HIGH or LOW

2) Parameter guaranteed by design (*) Voltage range is 3.3V

± 0.3V

Symbol

Parameter

Test Condition

Value

Unit

VCC

(V)

TA = 25°C

-40 to 85°C

-55 to 125°C

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

VOLP

Dynamic Low Voltage

Quiet Output (note 1, 2)

3.3

CL = 50 pF

0.3

0.8

V

VOLV

-0.8

-0.3

VIHD

Dynamic High Voltage

Input (note 1, 3)

3.3

2

VILD

Dynamic Low Voltage

Input (note 1, 3)

3.3

0.8

Symbol

Parameter

Test Condition

Value

Unit

VCC

(V)

CL

(pF)

TA = 25°C

-40 to 85°C

-55 to 125°C

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

tPLH tPHL Propagation Delay

Time CLOCK to Q

2.7

15

7.6

14.5

1.0

17.5

1.0

18.5

ns

2.7

50

10.1

18.0

1.0

21.0

1.0

22.0

3.3(*)

15

5.9

9.3

1.0

11.0

1.0

12.0

3.3(*)

50

8.4

12.8

1.0

14.5

1.0

15.5

tPLH tPHL Propagation Delay

Time CLEAR to Q

2.7

15

7.9

15.0

1.0

18.5

1.0

19.5

ns

2.7

50

10.4

18.5

1.0

22.0

1.0

23.0

3.3(*)

15

6.2

9.7

1.0

11.5

1.0

12.5

3.3(*)

50

8.7

13.2

1.0

15.0

1.0

16.0

tWL

CLEAR pulse

Width, HIGH

2.7

6.5

7.5

ns

3.3(*)

5.0

tW

CLOCK pulse

Width

2.7

6.5

7.5

ns

3.3(*)

5.0

tS

Setup Time Q to

CLOCK HIGH or

LOW

2.7

7.5

8.5

ns

3.3(*)

5.0

6.0

th

Hold Time Q to

CLOCK HIGH or

LOW

2.7

0.0

ns

3.3(*)

0.0

tREM

Recovery Time

CLEAR to Q

2.7

4.5

ns

3.3(*)

3.0

fMAX

Maximum Clock

Frequency

2.7

15

65

130

55

MHz

2.7

50

45

60

40

3.3(*)

15

115

180

95

3.3(*)

50

65

95

55

tOSLH

tOSHL

Output To Output

Skew Time (note1,

2)

2.7

50

0.5

1.0

1.5

ns

3.3(*)

50

0.5

1.0

1.5

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