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STA014B Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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STA014B Scheda tecnica(HTML) 10 Page - STMicroelectronics |
10 / 45 page SCLK_POL=0 SCLK_POL=4 DATA IGNORED DATA VALID SCKR SCKR SDI BIT_EN D98AU968A DATA IGNORED Figure 8. Serial Input Interface Clocks 3. INTERFACE DESCRIPTION 3.1 - Serial Input Interface STA014 receives the input data (MSB first) through the Serial Input Interface (Fig.7). It is a serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Se- rial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock. The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. For proper operation BIT_EN line should be toggled only when SCKR is stable low (for both SCLK_POL configuration)8The possible configurations are described in Fig. 8. 3.2 - GPSO Output Interface In order to retrieve ADPCM encoded data a Gen- eral Purpose Serial Output interface is available (in TQFP44 and LFBGA64 packages only). The maximum frequency for GPSO_SCKR clock is the DSP system clock frequency divided by 3 (i.e. 8.192 MHz @ 24.58MHz). The interface is based on a simple and configurable 3-lines proto- col, as described by figure 10. 3.3 - PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following sig- nals: SDO PCM Serial Data Output SCKT PCM Serial Clock Output LRCLK Left/Right Channel Selection Clock The output samples precision is selectable from 16 to 24 bits/word, by setting the output precision with PCMCONF (16, 18, 20 and 24 bits mode) register. Data can be output either with the most significant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the several STA014 PCM Output Formats. The sample rates set decoded by STA014 is described in Table 1. LRCKT SDO SDO PCM_FORMAT = 0 PCM_DIFF = 0 PCM_FORMAT = 1 PCM_DIFF = 1 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles M S M S L S L S L S L S M S M S M S L S M S L S L S L S M S M S LRCKT SDO SDO PCM_ORD = 1 PCM_PREC is 16 bit mode PCM_ORD = 0 PCM_PREC is 16 bit mode 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles M S M S L S L S L S L S M S M S M S L S M S L S L S L S M S M S SDO PCM_FORMAT = 0 PCM_DIFF = 1 L S L S M S M S M S L S L S M S SDO PCM_FORMAT = 1 PCM_DIFF = 1 L S L S M S M S M S L S L S M S 0 0 0 0 0 0 0 0 00 00 0 0 0 0 MSB MSB MSB MSB Figure 9. PCM Output Formats Table 1: MPEG Sampling Rates (KHz) MPEG 1 MPEG 2 MPEG 2.5 48 24 12 44.1 22.05 11.025 32 16 8 STA014-STA014B-STA014T 10/45 |
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