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ST92F120JV9Q Scheda tecnica(PDF) 7 Page - STMicroelectronics

Il numero della parte ST92F120JV9Q
Spiegazioni elettronici  8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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ST92F120 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92F120 microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The new-generation ST9 MCU
devices now also support low power consumption
and low voltage operation for power-efficient and
low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows a single linear ad-
dress space of up to 4 Mbytes.
Four independent buses are controlled by the
Core: a 16-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
core.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
The powerful I/O capabilities demanded by micro-
controller
applications
are
fulfilled
by
the
ST92F120 with 48 (TQFP64) or 77 (PQFP100) I/O
lines dedicated to digital Input/Output. These lines
are grouped into up to ten 8-bit I/O Ports and can
be configured on a bit basis under software control
to provide timing, status signals, an address/data
bus for interfacing to the external memory, timer
inputs and outputs, analog inputs, external inter-
rupts and serial or parallel I/O. Two memory spac-
es are available to support this wide range of con-
figurations: a combined Program/Data Memory
Space and the internal Register File, which in-
cludes the control and status registers of the on-
chip peripherals.
1.1.2 External Memory Interface
PQFP100 devices have a 16-bit external address
bus allowing them to address up to 64K bytes of
external memory. TQFP64 devices have an 11-bit
external address bus for addressing up to 2K
bytes.
1.1.3 On-chip Peripherals
Two 16-bit MultiFunction Timers, each with an 8
bit Prescaler and 12 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functions by the usage of the two associat-
ed DMA channels for each timer.
On PQFP100 devices, two Extended Function
Timers provide further timing and signal genera-
tion capabilities.
A Standard Timer can be used to generate a sta-
ble time base independent from the PLL.
An I2C interface provides fast I2C and Access Bus
support.
The SPI is a synchronous serial interface for Mas-
ter and Slave device communication. It supports
single master and multimaster systems.
A J1850 Byte Level Protocol Decoder is available
(on some devices only) for communicating with a
J1850 network.
In addition, there is an 16 channel Analog to Digital
Converters with integral sample and hold, fast
conversion time and 8-bit resolution. In the
TQFP64 version only 8 input channels are availa-
ble.
Completing the device are two or one full duplex
Serial Communications Interfaces with an integral
generator, asynchronous and synchronous capa-
bility (fully programmable format) and associated
address/wake-up option, plus two DMA channels.
Finally, a programmable PLL Clock Generator al-
lows the usage of standard 3 to 5 MHz crystals to
obtain a large range of internal frequencies up to
24MHz. Low power Run (SLOW), Wait For Inter-
rupt, low power Wait For Interrupt, STOP and
HALT modes are also available.
9


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