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ST5092AD Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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ST5092AD Scheda tecnica(HTML) 5 Page - STMicroelectronics |
5 / 29 page FUNCTIONAL DESCRIPTION I DEVICE OPERATION I.1 Power on initialization: When power is first applied, power on reset cir- cuitry initializes ST5092 and puts it into the power down state. Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the Control Register description section. All CODEC functions are disabled. The desired selection for all programmable func- tions may be intialized prior to a power up com- mand using the MICROWIRE control channel. I.2 Power up/down control: Following power-on initialization, power up and power down control may be accomplished by writ- ing any of the control instructions listed in Table 1 into ST5092 with ”P” bit set to 0 for power up or 1 for power down. Normally, it is recommended that all programma- ble functions be initially programmed while the device is powered down. Power state control can then be included with the last programming in- struction or in a separate single byte instruction. Any of the programmable registers may also be modified while ST5092 is powered up or down by setting ”P” bit as indicated. When power up or down control is entered as a single byte instruc- tion, bit 1 must be set to a 0. When a power up command is given, all de-acti- vated circuits are activated, but output DX will re- main in the high impedance state until the second Fs pulse after power up. I.3 Power down state: Following a period of activity, power down state may be reentered by writing a power down in- struction. Control Registers remain in their current state and can be changed by MICROWIRE control inter- face. In addition to the power down instruction, detec- tion of loss MCLK (no transition detected) auto- matically enters the device in ”reset” power down state with DX output in the high impedance state. I.4 Transmit section: Transmit analog interface is designed in two stages to enable gains up to 42.5 dB to be real- ized. Stage 1 is a low noise differential amplifier providing 20 dB gain. A microphone may be ca- pacitevely connected to MIC1+, MIC1- inputs, while the MIC2+ MIC2– and MIC3+ MIC3- inputs may be used to capacitively connect a second mi- crophone or a third microphone respectively or an auxiliary audio circuit. MIC1 or MIC2 or MC3 or transmit mute is selected with bits 6 and 7 of reg- ister CR4. In the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. Following the first stage is a programmable gain amplifier which provides from 0 to 22.5 dB of ad- ditional gain in 1.5dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal 0 dBm0 voltage is 0.49 Vrms (overload level is 0.7 Vrms). Second stage amplifier gain can be pro- grammed with bits 4 to 7 of CR5. An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter can be either a 14-bit linear (bit CM = 0 in register CR0) or can have a compressing characteristics (bit CM = 1 in register CR0) according to CCITT A or MU255 coding laws. A precision on chip volt- age reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an in- ternal autozero circuit. Each encode cycle begins immediatly at the be- ginning of the selected Transmit time slot. The to- tal signal delay referenced to the start of the time slot is approximatively 195 µs (due to the transmit filter) plus 125 µs (due to encoding delay), which totals 320 µs. Voice data is shifted out on DX dur- ing the selected time slot on the transmit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de- layed reverse mode. I.5 Receive section: Voice Data is shifted into the decoder’s Receive voice data Register via the DR pin during the se- lected time slot on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in non-delayed reverse mode. The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decod- ing characteristic. Following the Decoder is a 3400 Hz 8th order band-pass switched capacitor filter with integral Sin X/X correction for the 8 kHz sample and hold. 0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A tran- scient suppressing circuitry ensure interference noise suppression at power up. The analog speech signal output can be routed either to earpiece (VFR+,VFR- outputs) or to an ex- tra analog output (VLr+,VLr- outputs) by setting bits OE and SE (1 and 0 of CR4). Total signal delay is approximatively 190 µs (filter plus decoding delay) plus 62.5 µs (1/2 frame) which gives approximatively 252 µs. Differential outputs VFR+,VFR- are intended to di- rectly drive an earpiece. Preceding the outputs is a programmable attenuation amplifier, which must ST5092 5/29 |
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