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ST5090AD Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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ST5090AD Scheda tecnica(HTML) 3 Page - STMicroelectronics |
3 / 29 page PIN FUNCTIONS (SO28) Pin Name Description 1 N.C. Not Connected. 2VCCA Positive power supply input for the analog section. +5V ±10% or 3.3V ±10% selectable. VCC and VCCA must be directly connected together. 3VCCP Positive power supply input for the power section. 5V ±10% or 3.3V ±10% selectable VCCP and VCC must be connected together. 4 N.C. Not Connected. 5,6 VFr+,VFr– Receive analog earpiece amplifier complementary outputs. These outputs can drive directly earpiece transductor. The signal at this output can be the sum of: - Receive Speech signal from DR, - Internal Tone Generator, - Sidetone signal. 7,8 VLr+,VLr– Receive analog extra amplifier complementary outputs. The signal at these outputs can be the sum of: - Receive Speech signal from DR, - Internal Tone generator, - Sidetone signal. 9 GNDP Power ground. VFr and VLr driver are referenced to this pin. GNDP and GND must be connected together close to the device. 10 DR Receive data input: Data is shifted in during the assigned Received time slots In delayed and non- delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is shifted in at the MCLK frequency on the rising edges of MCLK. 11 CCLK Control Clock input: This clock shifts serial control information into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 12 CS- Chip Select input: When this pin is low, control information is written into and out from the ST5090 via CI and CO pins. 13 CI Control data Input: Serial Control information is shifted into the ST5090 on this pin when CS- is low on the rising edges of CCLK. 14 BZ Pulse width modulated buzzer driver output. 15 VCC Positive power supply input for the digital section. +5V ±10% or 3.3V ±10% selectable. 16 CO Control data Output: Serial control/status information is shifted out from the ST5090 on this pin when CS- is low on the falling edges of CCLK. 17 DX Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere DX output is in the high impedance state. In delayed and non-delayed normal frame synchr. modes, voice data byte is shifted out from TRISTATE output DX at the MCLK on the rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted out on the falling edge of MCLK. 18 GND Ground: All digital signals are referenced to this pin. 19 FS Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive frames. Any of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. 20 MCLK Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CRO. MCLK is used also to shift-in and out data. 21 LO A logic 1 written into DO (CR1) appears at LO pin as a logic 0 A logic 0 written into DO (CR1) appears at LO pin as a logic 1. 22 MIC2- Second negative high impedance input to transmit pre-amplifier for microphone connection. 23 MIC2+ Second Positive high impedance input to transmit pre-amplifier for microphone connection. 24 MIC1- Negative high impedance input to transmit pre-amplifier for microphone connection. 25 MIC1+ Positive high impedance input to transmit pre-amplifier for microphone connection. 26 GNDA Analog Ground: All analog signals are referenced to this pin. GND and GNDA must be connected together close to the device. 27 MIC3- Third negative high impedance output to transmit preamplifier for microphone connection. 28 MIC3+ Third positive high impedance output to transmit preamplifier for microphone connection. ST5090 3/29 |
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