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ST5080D Scheda tecnica(PDF) 7 Page - STMicroelectronics |
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ST5080D Scheda tecnica(HTML) 7 Page - STMicroelectronics |
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7 / 32 page  FUNCTIONAL DESCRIPTION Power on initialization: When power is first applied, power on reset cicuitry initializes PIAFE and puts it into the power down state. Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the Control Register description section. All CODEC functions are disabled. Digital Interface is configured in GCI mode or in COMBO I/II mode depending on Mode Select pin connection. The desired selection for all programmable func- tions may be intialized prior to a power up com- mand using Monitor channel in GCI mode or MI- CROWIRE port in COMBO I/II mode. Power up/down control: Following power-on initialization, power up and power down control may be accomplished by writ- ing any of the control instructions listed in Table 1 into PIAFE with ”P” bit set to 0 for power up or 1 for power down. Normally, it is recommended that all programma- ble functions be initially programmed while the device is powered down. Power state control can then be included with the last programming in- struction or in a separate single byte instruction. Any of the programmable registers may also be modified while ST5080A is powered up or down by setting ”P” bit as indicated. When power up or down control is entered as a single byte instruc- tion, bit 1 must be set to a 0. When a power up command is given, all de-acti- vated circuits are activated, but output DX will re- main in the high impedance state on B time slots until the second Fs pulse after power up, even if a B channel is selected. Power down state: Following a period of activity, power down state may be reentered by writing a power down in- struction. Control Registers remain in their current state and can be changed either by MICROWIRE control in- terface or GCI control channel depending on mode selected. In addition to the power down instruction, detec- tion of loss MCLK (no transition detected) auto- matically enters the device in ”reset” power down state with DX output in the high impedance state and L0 in high impedance state. Transmit section: Transmit analog interface is designed in two stages to enable gains up to 35 dB to be realized. Stage 1 is a low noise differential amplifier provid- ing 20 dB gain. A microphone may be ca- pacitevely connected to MIC1+, MIC1- inputs, while the MIC2+ MIC2– inputs may be used to capacitively connect a second microphone (for digital handsfree operation) or an auxiliary audio circuit such as TEA 7540 Hands-free circuit. MIC1 or MIC2 source is selected with bit 7 of register CR4. Following the first stage is a programmable gain amplifier which provides from 0 to 15 dB of addi- tional gain in 1 dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal 0 dBmO voltage is 0.739 V (overload level is 1.06 Vrms). Second stage amplifier can be pro- grammed with bits 4 to 7 of CR5. To temporarily mute the transmit input, bit TE (6 of CR4) may be set low. In this case, the analog transmit signal is grounded and the sidetone path is also disabled. An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter has a compressing characteristic according to CCITT A or mu255 coding laws, which must be selected by setting bits MA, IA in register CR0. A precision on chip voltage reference ensures accu- rate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an in- ternal autozero circuit. Each encode cycle begins immediatly at the be- ginning of the selected Transmit time slot. The to- tal signal delay referenced to the start of the time slot is approximatively 195 µs (due to the transmit filter) plus 123 µs (due to encoding delay), which totals 320 µs. Voice data is shifted out on DX dur- ing the selected time slot on the transmit rising adges of MCLK. Receive section: Voice Data is shifted into the decoder’s Receive voice data Register via the DR pin during the se- lected time slot on the 8 receive edges of MCLK. The decoder consists of an expanding DAC with either A or MU255 law decoding characteristic which is selected by the same control instruction used to select the Encode law during intitializa- tion. Following the Decoder is a 3400 Hz 6th or- der low pass switched capacitor filter with integral Sin X/X correction for the 8 kHz sample and hold. 0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A tran- scient suppressing circuitry ensure interference noise suppression at power up. The analog speech signal output can be routed either to earpiece (VFR+,VFR- outputs) or to loud- speaker (LS+, LS- outputs) by setting bits SL and SE (1 and 0 of CR4). Total signal delay is approximatively 190 µs (filter plus decoding delay) plus 62.5 µs (1/2 frame) which gives approximatively 252 µs. Differential outputs VFR+,VFR- are intended to di- ST5080A 7/32 |
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