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ST486DX Scheda tecnica(PDF) 3 Page - STMicroelectronics |
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ST486DX Scheda tecnica(HTML) 3 Page - STMicroelectronics |
3 / 34 page 1. SMM OVERVIEW 1.1 Introduction This Programmer’s Guide has been written to aid programmers in the creation of software using the SGS-Thomson System Management Mode (SMM) for ST486DX CPUs. This guide should be used in conjunction with the SGS-Thomson ST486DX and ST486DX2 Processors Data Book. SMM programming related to the ST486SLC/e is covered in the ST486SLC/e SMM Programmer’s Guide. SMM provides the system designer with another processor operating mode. Within this document the standard x86 operating modes (real, v86 and protected) are referred to as normal mode. Nor- mal mode operation can be interrupted by an SMI interrupt or special instruction that places the processor in System Management Mode (SMM). SMM can be used to enhance the functionality of the system by providing power management, register shadowing, peripheral emulation and other system level functions. SMM can be totally transparent to all application software, including pro- tected mode operating systems. 1.2 SGS-Thomson SMM Features SMM operation within one of the SGS-Thomson ST486DX microprocessors is similar to related operations performed by other x86 microprocessors. All processors with SMM capability, switch into real mode upon entry into the SMM interrupt handler. Each CPU has a unique SMM code lo- cations. However, the SMM memory region for the SGS-Thomson CPU has a programmable loca- tion and size. All devices save some of the CPU registers upon entry to SMM. The SGS-Thomson CPU automatically saves minimal register information reducing the entry and exit clock count to as low as 100 clock cycles. This compares with Intel’s clock overhead for a typical entry and exit of 633 clock cycles. The SGS-Thomson SMM implementation provides unique instructions that save additional segment registers as required by the programmer. The x86 MOV instruction can be used to save the general purpose registers. Although all SMM capable CPUs provide I/O trapping, the SGS-Thomson CPUs simplify I/O type identification and instruction restarting. SGS-Thomson CPUs also make available to the SMM rou- tine information which can simplify peripheral register shadowing. SGS-Thomson provides a method to prevent SMM configuration registers from being accessed by applications. Access to the SMM configuration can be prevented by setting a bit in the CPU con- figuration space. Not allowing an application to disable or alter SMM operation is useful for anti- virus or security measures. ST486DX - SMM OVERVIEW 9 |
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