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ST18952X66S Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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ST18952X66S Scheda tecnica(HTML) 10 Page - STMicroelectronics |
10 / 67 page 10/66 ST18952 D950Core The D950Core is a general purpose programmable 16-bit fixed point Digital Signal Processor Core. The main blocks of the D950Core include an arithmetic data calculation unit, a program control unit and an address calculation unit, able to manage up to 64k (program) and 128k (data) x 16-bit memory spaces. Memory One 32 Kword and two 8 Kword single port memories are included on-chip: • 32 Kword instruction memory on I space • 8 Kword X-Data memory on X space • 8 Kword Y-Data memory on Y space One 512 word dual port memory is shared on X and Y spaces. Memory can be extended off-chip for all three spaces in two ways: 1: Directly - Accesses to program and data memories can be performed simulta- neously. Insertion of wait-states is necessary in case of nominal frequency work. 2: Through the bus switch unit - Accesses to the different external spaces are mul- tiplexed and wait-states are added. Bus switch unit The bus switch unit (BSU) is a bi-directional switcher which switches the 3 internal buses (I, X and Y) to the external (E) bus. DMA controller The DMA controller manages data transfer between memories and external peripherals. There are four independent DMA channels. Transfers can occur on X/Y/I spaces (simultaneous transfers on X and Y spaces). Interrupt controller The interrupt controller (ITC) can manage up to eight external interrupts. Each source can be individually activated and programmed as edge or level triggered. A ‘pending interrupt’ flag displays the source waiting for service (this flag is writable to allow a software interrupt capability). The priority of interrupts is programmable. Timers There are two timer (TIM) units on the ST18952. The timers enable interrupts to be generated after predefined periods of time. |
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