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ST18952 Scheda tecnica(PDF) 6 Page - STMicroelectronics |
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ST18952 Scheda tecnica(HTML) 6 Page - STMicroelectronics |
6 / 67 page 6/66 ST18952 Table 2.4 General purpose parallel port / Interrupt requests (8 pins) Table 2.5 Clocks (6 pins) Table 2.6 Bus control (3 pins) Pin name Type Description P_ITRQ0-7 I/O Multiplexed input/output. Parallel port I/O or external interrupt request (ITRQ). Pin name Type Description EXTAL I Oscillator input. XTAL O Oscillator output. Nominal oscillator frequency is 27 MHz. MCLK I Master clock input (use of external clock generator). CLK_MODE I Clock mode select input. When low the oscillator and internal PLL are enabled. The 950 receives its Master clock from the PLL at 5 times the oscillator frequency. When high the PLL is disabled. The D950 receives its master clock from MCLK. INCYCLE O Instruction cycle. Asserted high for 1 CLKOUT cycle at the beginning of instruction cycle. CLKOUT O Output clock (at input clock/2 frequency). Pin name Type Description DTACK I Data transfer acknowledge input. Active low. It is combined in a OR gate with BSU DTACK output in order to generate the DTACK signal for the D950Core. It controls extension of bus cycles by inser- tion of wait-states when using external memory either through Bus-switch or direct extension. HOLD I External Bus Hold request input. Active low. HOLDACK O Hold acknowledge output. Active low. |
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