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ST10R167 Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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ST10R167 Scheda tecnica(HTML) 10 Page - STMicroelectronics |
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10 / 63 page  ST10R167 10/63 III - FUNCTIONAL DESCRIPTION The architecture of the ST10R167 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth inter- nal bus structure of the ST10R167. Figure 3 : Block diagram Port 6 Port 5 Port 3 BRG CPU-Core Internal RAM Watchdog Interrupt Controller 32 16 PEC 16 16 CAN Port 7 Port 8 BRG OSC. 2K Byte 16 16 16 ROMLESS XRAM XTAL1 XTAL2 CAN_RXD CAN_TXD External Memory 8 16 16 8 15 8 8 16 |
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