CDCE72010 datasheet(1/70 Pages) TI

Il numero della parte	CDCE72010

Spiegazioni elettronici	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

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Produttore elettronici	TI [Texas Instruments]

Homepage	http://www.ti.com

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FEATURES

APPLICATIONS

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

• Wide Charge-Pump Current Range From

200

µA to 3mA

• High Performance LVPECL, LVDS, LVCMOS

PLL Clock Synchronizer

• Dedicated Charge-Pump Supply for Wide

Tuning Voltage Range VCOs

• Two Reference Clock Inputs (Primary and

Secondary Clock) for Redundancy Support

• Presets Charge-Pump to V

CC_CP/2 for Fast

with Manual or Automatic Selection

Center-Frequency Setting of VC(X)O,

Controlled Via the SPI Bus

• Accepts Two Differential Input (LVPECL or

LVDS) References up to 500MHz (or Two

• SERDES Startup Mode (Depending on VCXO

LVCMOS Inputs up to 250MHz) as PLL

Range)

Reference

• Auxiliary Input: Output 9 can Serve as 2nd

• VCXO_IN Clock is Synchronized to One of Two

VCXO Input to Drive All Outputs or to Serve as

Reference Clocks

PLL Feedback Signal

• VCXO_IN Frequencies up to 1.5GHz (LVPECL)

• RESET or HOLD Input Pin to Serve as Reset or

800Mhz for LVDS and 250MHz for LVCMOS

Hold Functions

Level Signaling

• REFERENCE SELECT for Manual Select

• Outputs Can be a Combination of LVPECL,

Between Primary and Secondary Reference

LVDS, and LVCMOS (Up to 10 Differential

Clocks

LVPECL or LVDS Outputs or up to 20 LVCMOS

• POWER DOWN (PD) to Put Device in Standby

Outputs), Output 9 can be Converted to an

Mode

Auxiliary Input as a 2nd VC(X)O.

• Analog and Digital PLL Lock Indicator

• Output Divider is Selectable to Divide by 1, 2,

• Internally Generated VBB Bias Voltages for

3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36,

Single-Ended Input Signals

40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each

• Frequency Hold-Over Mode Activated by

Output Individually up to Eight Dividers.

HOLD Pin or SPI Bus to Improve Fail-Safe

(Except for Output 0 and 9, Output 0 Follows

Operation

Output 1 Divider and Output 9 Follows Output

• Input to All Outputs Skew Control

8 Divider)

• Individual Skew Control for Each Output with

• SPI Controllable Device Setting

Each Output Divider

• Individual Output Enable Control via SPI

• Packaged in a QFN-64 Package

Interface

• ESD Protection Exceeds 2kV HBM

• Integrated On-Chip Non-Volatile Memory

(EEPROM) to Store Settings without the Need

• Industrial Temperature Range of –40°C to 85°

to Apply High Voltage to the Device

• Optional Configuration Pins to Select Between

• Low Jitter Clock Driver for High-End Telecom

Two Default Settings Stored in EEPROM

and Wireless Applications

• Efficient Jitter Cleaning from Low PLL Loop

• High Precision Test Equipment

Bandwidth

• Very Low Phase Noise PLL Core

• Programmable Phase Offset (Input Reference

to Outputs)

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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