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CAT24AA02WI-10 Scheda tecnica(PDF) 2 Page - Catalyst Semiconductor

Il numero della parte CAT24AA02WI-10
Spiegazioni elettronici  1-Kb and 2-Kb I2C CMOS Serial EEPROM
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Produttore elettronici  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

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CAT24AA01, CAT24AA02
Doc. No. MD-1120 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Ratings
Units
Storage Temperature
–65 to +150
ºC
Voltage on any Pin with Respect to Ground
(2)
–0.5 to +6.5
V
REABILITY CHARACTERISTICS
(3)
Symbol
Parameter
Min
Units
NEND
(4)
Endurance
1,000,000
Program/Erase Cycles
TDR
Data Retention
100
Years
D.C. OPERATING CHARACTERISTICS
VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
0.5
mA
ICCW
Write Current
Write
1
mA
ISB
Standby Current
All I/O Pins at GND or VCC
1
μA
IL
I/O Pin Leakage
Pin at GND or VCC
1
μA
VIL
Input Low Voltage
-0.5
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.7 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
Max
Units
CIN
(3)
SDA I/O Pin Capacitance
VIN = 0V
8
pF
CIN
(3)
Input Capacitance (other pins)
VIN = 0V
6
pF
VIN < VIH
100
IWP
(5)
WP Input Current
VIN > VIH
1
μA
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode @ 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.


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