Motore di ricerca datesheet componenti elettronici |
|
RIVA128ZX Scheda tecnica(PDF) 10 Page - STMicroelectronics |
|
RIVA128ZX Scheda tecnica(HTML) 10 Page - STMicroelectronics |
10 / 85 page 128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX 10/85 3 OVERVIEW OF THE RIVA128ZX The RIVA128ZX is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D per- formance, meeting all the requirements of the mainstream PC graphics market and Microsoft’s PC’97. The RIVA128ZX introduces the most ad- vanced Direct3D ™ acceleration solution and also delivers leadership VGA, 2D and Video perfor- mance, enabling a range of applications from 3D games through to DVD, Intercast ™ and video con- ferencing. 3.1 BALANCED PC SYSTEM The RIVA128ZX is designed to leverage existing PC system resources such as system memory, high bandwidth internal buses and bus master ca- pabilities. The synergy between the RIVA128ZX graphics pipeline architecture and that of the cur- rent generation PCI and next generation AGP plat- forms, defines ground breaking performance lev- els at the cost point currently required for main- stream PC graphics solutions. Execute versus DMA models The RIVA128ZX is architected to optimize PC sys- tem resources in a manner consistent with the AGP “Execute” model. In this model texture map data for 3D applications is stored in system mem- ory and individual texels are accessed as needed by the graphics pipeline. This is a significant en- hancement over the DMA model where entire tex- ture maps are transferred into off-screen frame- buffer memory. The advantages of the Execute versus the DMA model are: • Improved system performance since only the required texels and not the entire texture map, cross the bus. • Substantial cost savings since all the frame- buffer is usable for the displayed screen and Z buffer and no part of it is required to be dedicat- ed to texture storage or texture caching. • There is no software overhead in the Direct3D driver to manage texture caching between ap- plication memory and the framebuffer. To extend the advantages of the Execute model, the RIVA128ZX’s proprietary texture cache and virtual DMA bus master design overcomes the bandwidth limitation of PCI, by sustaining a high texel throughput with minimum bus utilization. The host interface supports burst transactions up to 133MHz and provides over 400MBytes/s on AGP. AGP accesses offer other performance enhance- ments since they are from non-cacheable memory (no snoop) and can be low priority to prevent pro- cessor stalls, or high priority to prevent graphics engine stalls. Building a balanced system RIVA128ZX is architected to provide the level of 3D graphics performance and quality available in top arcade platforms. To provide comparable scene complexity in the 1997 time-frame, proces- sors will have to achieve new levels of floating point performance. Profiles have shown that 1997 mainstream CPUs will be able to transform over 1 million lit, meshed triangles/s at 50% utilization us- ing Direct3D. This represents an order of magni- tude performance increase over anything attain- able in 1996 PC games. To build a balanced system the graphics pipeline must match the CPU’s performance. It must be ca- pable of rendering at least 1 million polygons/s in order to avoid CPU stalls. Factors affecting this system balance include: • Direct3D compatibility. Minimizing the differ- ences between the hardware interface and the Direct3D data structures. • Triangle setup. Minimizing the number of for- mat conversions and delta calculations done by the CPU. • Display-list processing. Avoiding CPU stalls by allowing the graphics pipeline to execute inde- pendently of the CPU. • Vertex caching. Avoids saturating the host in- terface with repeated vertices, lowering the traf- fic on the bus and reducing system memory col- lisions. • Host interface performance. 3.2 HOST INTERFACE The host interface boosts communication between the host CPU and the RIVA128ZX. The optimized interface performs burst DMA bus mastering for efficient and fast data transfer. • 32-bit PCI version 2.1 or AGP version 1.0 • Burst DMA Master and target • 33MHz PCI clock rate, 66MHz AGP clock rate and AGP 2X mode • Supports over 100MBytes/s with 33MHz PCI to over 400MBytes/s on AGP 2X mode • Implements read buffer posting on AGP |
Codice articolo simile - RIVA128ZX |
|
Descrizione simile - RIVA128ZX |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |