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RIVA128 Scheda tecnica(PDF) 7 Page - STMicroelectronics |
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RIVA128 Scheda tecnica(HTML) 7 Page - STMicroelectronics |
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7 / 77 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 7/77 PCICBE[3:0]# I/O Multiplexed bus command and byte enable signals. During the address phase of a trans- action PCICBE[3:0]# define the bus command, during the data phase PCICBE[3:0]# are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain valid data. PCICBE[0]# applies to byte 0 (LSB) and PCICBE[3]# applies to byte 3 (MSB). When connected to AGP these signals carry different commands than PCI when requests are being enqueued using AGPPIPE#. Valid byte information is provided during AGP write transactions. PCICBE[3:0]# are not used during the return of AGP read data. PCIPAR I/O Parity. This signal is the even parity bit generated across PCIAD[31:0] and PCICBE[3:0]#. PCIPAR is stable and valid one clock after the address phase. For data phases PCIPAR is stable and valid one clock after either PCIIRDY# is asserted on a write transaction or PCITRDY# is asserted on a read transaction. Once PCIPAR is valid, it remains valid until one clock after completion of the current data phase. The master drives PCIPAR for address and write data phases; the target drives PCIPAR for read data phases. PCIFRAME# I/O Cycle frame. This signal is driven by the current master to indicate the beginning of an access and its duration. PCIFRAME# is asserted to indicate that a bus transaction is beginning. Data transfers continue while PCIFRAME# is asserted. When PCIFRAME# is deasserted, the transaction is in the final data phase. PCIIRDY# I/O Initiator ready. This signal indicates the initiator’s (bus master’s) ability to complete the cur- rent data phase of the transaction. See extended description for PCITRDY#. When connected to AGP this signal indicates the initiator (AGP compliant master) is ready to provide all write data for the current transaction. Once PCIIRDY# is asserted for a write operation, the master is not allowed to insert wait states. The assertion of PCIIRDY# for reads, indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers. PCITRDY# I/O Target ready. This signal indicates the target’s (selected device’s) ability to complete the current data phase of the transaction. PCITRDY# is used in conjunction with PCIIRDY#. A data phase is completed on any clock when both PCITRDY# and PCIIRDY# are sampled as being asserted. During a read, PCITRDY# indicates that valid data is present on PCIAD[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both PCIIRDY# and PCITRDY# are asserted together. When connected to AGP this signal indicates the AGP compliant target is ready to provide read data for the entire transaction (when transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data, when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfers on both read and write transactions. PCISTOP# I/O PCISTOP# indicates that the current target is requesting the master to terminate the cur- rent transaction. PCIIDSEL I Initialization device select. This signal is used as a chip select during configuration read and write transactions. For AGP applications note that IDSEL is not a pin on the AGP connector. The RIVA 128 performs the device select decode internally within its host interface. It is not required to connect the AD16 signal to the IDSEL pin as suggested in the AGP specification. PCIDEVSEL# I/O Device select. When acting as an output PCIDEVSEL# indicates that the RIVA 128 has decoded the PCI address and is claiming the current access as the target. As an input PCIDEVSEL# indicates whether any other device on the bus has been selected. PCIREQ# O Request. This signal is asserted by the RIVA 128 to indicate to the arbiter that it desires to become master of the bus. Signal I/O Description |
Codice articolo simile - RIVA128 |
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