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UC2914DWG4 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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UC2914DWG4 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 24 page UC2914 UC3914 SLUS425C − DECEMBER 2003 − REVISED JULY 2004 11 www.ti.com APPLICATION INFORMATION UDG−97055 Figure 4. Typical Timing Diagram Using Latch Reset (LR) Function Table 2. Fault Timing Conditions with Latch Reset Function TIME CONDITION t0 Normal conditions. Output current is nominal, output voltage is at positive rail, VCC t1 Fault control reached. Output current rises above the programmed fault value, CT begins to charge at 100-µA + IPL. t2 Maximum current reached. Output current reaches the programmed maximum level and becomes a constant cur- rent with value IMAX. t3 Fault occurs. CT has charged to 2.5 V, fault output goes low, the FET turns off allowing no output current to flow, VVOUTS discharges to GND. t4 Reset comparator threshold reached but no retry since LR pin held high. t5 LR toggled low, N-channel MOSFET turned on and sources current to load. t6=t3 t7 LR toggled low before VCT reaches reset comparator threshold, causing retry. t8 Since LR toggled low during present cycle, N-channel MOSFET turned on and sources current to load. t9=t0 Fault released, normal condition. Return to normal operation of the load. |
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