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CS5460 Scheda tecnica(PDF) 7 Page - Cirrus Logic |
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CS5460 Scheda tecnica(HTML) 7 Page - Cirrus Logic |
7 / 34 page CS5460 DS279PP5 7 SWITCHING CHARACTERISTICS (T A = -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF)) Notes: 14. Device parameters are specified with a 4.096 MHz clock, however, clocks between 3MHz to 20 MHz can be used. 15. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec. 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Gate Oscillator (Note 14) MCLK 2.5 4.096 20 MHz Master Clock Duty Cycle 40 - 60 % CPUCLK Duty Cycle (Note 15) 40 60 % Rise Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output trise - - - - - 50 1.0 100 - µs µs ns Fall Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output tfall - - - - - 50 1.0 100 - µs µs ns Start-up Oscillator Start-up Time XTAL = 4.096 MHz (Note 17) tost -60 - ms Serial Port Timing Serial Clock Frequency SCLK - - 2 MHz Serial Clock Pulse Width High Pulse Width Low t1 t2 200 200 - - - - ns ns SDI Write Timing CS Enable to Valid Latch Clock t3 50 - - ns Data Set-up Time Prior to SCLK Rising t4 50 - - ns Data Hold Time After SCLK Rising t5 100 - - ns SCLK Falling Prior to CS Disable t6 100 - - ns SDO Read Timing CS Enable to Valid Latch Clock t7 -- 150 ns SCLK Falling to New Data Bit t8 -- 150 ns CS Rising to SDO Hi-Z t9 -- 150 ns |
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Descrizione simile - CS5460 |
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