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M74HC173 Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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M74HC173 Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 12 page M54HC173 M74HC173 October 1992 QUAD D-TYPE REGISTER (3-STATE) B1R (Plastic Package) ORDER CODES : M54HC173F1R M74HC173M1R M74HC173B1R M74HC173C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection DESCRIPTION . HIGH SPEED fMAX = 73 MHz (TYP.) at VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) at TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE |IOH|= IOL = 6 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS 173 The M54/74HC173 is a high speed CMOS QUAD D- TYPE REGISTER (3-STATE) fabricated in silicon gate C 2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device is composed of a four-bit register includ- ing D-type flip-flops and 3-state buffers. The four flip- flops are controlled by a common clock input (CLOCK) and a common reset input (CLEAR). Sig- nals applied to the data inputs (D1-D4) are stored at the respective flip-flops on the positive going transi- tion of the clock input, only when both clock control inputs (G1 and G2) are held low. The reset feature is asynchronous and active high. The stored data are provided on each output only when both output control inputs (M and N) are held low, otherwise the outputs go to the high-impedance state. All inputs are equipped with protection circuits against static discharge and transient excess volt- age. 1/12 |
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