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UC37136MG4 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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UC37136MG4 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 9 page UC27136, UC37136 DUAL OUTPUT SWITCH SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION TRUTHTABLE INV2 IN2 Switch 2 Low Low Off High Low On Low High On High High Off turn on delay The NPN output switches remains off until the external capacitor connected to CDEL charges up to the internal threshold voltage of 4 V with a charging current of 2.5 µA. This off condition is independent of the state of the input logic pins IN1, IN2, and INV2. This capacitor charging imparts a delay time on the outputs that is equal to approximately 1.6 ms/nF. As an example, a 0.1- µF capacitor connected to CDEL results in a 160 ms turnon delay after VCC crosses the 8-V UVLO threshold. If VCC drops below the 7.5-V hysteresis threshold, the CDEL capacitor is discharged immediately and both outputs turn off. The CDEL pin can also be externally driven low to restart the turnon delay sequence. The minimum acceptable value for the CDEL capacitor, when driving a capacitive load, is determined by: CDEL (MIN) + C LOAD V LOAD 2445 (1) Where CLOAD is equal to the output capacitive load and VLOAD is equal to the voltage rail of the output load. The maximum switching frequency to drive a capacitive load, CLOAD, is given by: f (MAX) + 1 9.4 CDEL 1 * e *C LOAD V LOAD 5 103 CDEL ) C LOAD V LOAD (2) overcurrent indication The open collector output SD pin can be used to drive an LED to signal when an overload condition is present. The LED turns on, through an external pullup, when the outputs are shut down due to an overcurrent. The maximum SD current is 8 mA. |
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