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M27W101-120K6TR Scheda tecnica(PDF) 5 Page - STMicroelectronics |
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M27W101-120K6TR Scheda tecnica(HTML) 5 Page - STMicroelectronics |
5 / 15 page 5/15 M27W101 Table 7. Read Mode DC Characteristics (1) (TA = –40 to 85°C; VCC = 2.7V to 3.6V; VPP =VCC) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA ICC Supply Current E= VIL,G = VIL, IOUT = 0mA, f = 5MHz, VCC ≤ 3.6V 15 mA ICC1 Supply Current (Standby) TTL E= VIH 1mA ICC2 Supply Current (Standby) CMOS E> VCC – 0.2V, VCC ≤ 3.6V 15 µA IPP Program Current VPP =VCC 10 µA VIL Input Low Voltage –0.6 0.2 VCC V VIH (2) Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage TTL IOH = –400µA 2.4 V Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the prima- ry device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1 µF ceram- ic capacitor be used on every device between VCC and VSS. This should be a high frequency capaci- tor of low inherent inductance and should be placed as close to the device as possible. In addi- tion, a 4.7 µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devic- es. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. |
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