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AMU2481 Scheda tecnica(PDF) 9 Page - Micronas |
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AMU2481 Scheda tecnica(HTML) 9 Page - Micronas |
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9 / 25 page  AMU 2481 MICRONAS INTERMETALL 9 2.2. DSP Block The AMU 2481 contains a complete mask–programma- ble digital signal processor with the blocks as described in the following sections. 2.2.1. C–RAM, C–ROM and Data RAM Coefficients and control parameters for digital process- ing of audio data are either fixed or variable by means of the CCU. The coefficient (C) memory is therefore di- vided into two parts: C–RAM, containing 32 locations of 8 bits each, which can be loaded by the CCU via the IM bus interface. The AMU software needs 32 variable parameters, and for proper processing all locations must be loaded with the corresponding values. C–ROM, containing 28 locations of 8 bits each, which are loaded with fixed values, required for the DSP soft- ware. For the user there is no possibility to change coeffi- cients in the C–ROM. Input data and intermediate re- sults can be stored in the AMU’s Data RAM whose locations have 16 bits each. This RAM is arranged in the following way: – 50 locations for intermediate results and output data – 4 locations for S bus input channels – 2 locations for 2 PDM channels from the decimation fil- ters 2.2.2. Program ROM, Program Counter and Control Block The DSP software of the AMU 2481 is stored in the pro- gram ROM. Its size is 256 14 bits, and its content can- not be modified by the user because it is mask–pro- grammed. Program ROM is addressed by the program counter (P.C.), which is a preset table counter. Instruction decoding and coordinating of all time func- tions is performed by the control block. Multiplexing of the two busses, addressing the coefficient memory and controlling the separator are also tasks of the control block. By means of the separator, data are transferred to the DACs. 2.2.3. Arithmetic Logic Unit (ALU) The core of the DSP block is the ALU. Multiplication of 16 8 bit, addition using a 20–bit accumulator, and shift operations are performed in the ALU. Accumulation is done according to a saturation characteristic (see sec- tion 3.1.). 2.3. System Clock ΦM and PDM Sampling Rate The clock at the AMU’s ΦM input is dependent on the current TV standard. The AMU is mainly provided for the German TV stereo system PAL and digital source stan- dard (e.g. D2–MAC). In all cases, the physical source of the AMU’s system clock is the DMA 2271 D2–MAC De- coder (Fig.1–2): Table 2–1: Selection of operation mode by k33 Mode k 33, Bit 6 PAL D2–MAC 0 1 1. For PAL mode, the system clock ΦM is derived from the color carrier frequency, for example in the MCU 2600 Clock Generator IC, and transferred to the DMA 2271 to be passed on to the AMU. In the ADC, as well as in the AMU, the ΦM clock is divided by four to produce the PDM rate, and by 128 to generate the sampling rate. 2. For digital source (S bus) operation, the AMU sys- tem clock ΦM is generated in the DMA 2271 in such a way that it is a multiple of the D2–MAC typical audio sampling frequency. The S bus signals S–Clock and S– Ident are then derived from this clock. Table 2–2 gives details about the clock requirements of the above operation modes. Selection of the operation mode (clock dividers) has to be transmitted by the CCU by means of coefficient k33, Bit 6 (see table 2–1, also section 3.13.). To enable parallel cascading of AMUs without external switches, (e.g. NICAM to SCART and D2MAC to TV) in the 44–PLCC package, the main clock (the S–Clock and the S–Ident, see section 2.1.2.2.) can be passed through the AMU 2481. The push–pull output can be switched to high impedance, which is the default status after power–on reset. To switch it on or off, use the same bit that controls the SBUS output: k33 bit3 = 0 outputs = active = 1 outputs = high impedance Table 2–2: AMU system clock ΦM and derived sampling rates TV Standard AMU ΦM PDM Rate Sampling Rate PAL D2–MAC 17.73 MHz 18.432 MHz :4 = 4.43 MHz – :128 = 34.63 kHz :576 = 32 kHz |
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