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LM3502 Scheda tecnica(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte LM3502
Spiegazioni elettronici  Step-Up Converter for White LED Applications
Download  18 Pages
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM3502 Scheda tecnica(HTML) 2 Page - National Semiconductor (TI)

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Connection Diagrams
10-Bump Thin MicroSMD
Package (TLP10)
16-Lead Thin Leadless Leadframe
Package (SQA16A)
20131702
TOP VIEW
20131703
TOP VIEW
Pin Descriptions/Functions
Bump #
Pin #
Name
Description
A1
9
Cntrl
Shutdown Control Connection
B1
7
Fb
Feedback Voltage Connection
C1
6
V
OUT2
Drain Connections of The NMOS and PMOS Field Effect Transistor (FET) Switches
(Figure 2: N2 and P1)
D1
4
V
OUT1
Over-Voltage Protection (OVP) and Source Connection of The PMOS FET Switch
(Figure 2: P1)
D2
2 and 3
Sw
Drain Connection of The Power NMOS Switch (Figure 2: N1)
D3
15 and 16
PGND
Power Ground Connection
C3
14
AGND
Analog Ground Connection
B3
13
V
IN
Supply or Input Voltage Connection
A3
12
En2
NMOS FET Switch Control Connection
A2
10
En1
PMOS FET Switch Control Connection
1
NC
No Connection
5
NC
No Connection
8
NC
No Connection
11
NC
No Connection
DAP
DAP
Die Attach Pad (DAP), must be soldered to the printed circuit board’s ground plane for
enhanced thermal dissipation.
Cntrl (Bump A1): Shutdown control pin. When V
Cntrl is
1.4V, the LM3502 is enabled or ON. When V
Cntrl is
≤ 0.3V,
the LM3502 will enter into shutdown mode operation. The
LM3502 has an internal pull down resistor on the Cntrl pin,
thus the device is normally in the off state or shutdown mode
of operation.
Fb (Bump B1): Output voltage feedback connection. The
white LED string network current is set/programmed using a
resistor from this pin to ground.
V
OUT2 (Bump C1): Drain connections of the internal PMOS
and NMOS FET switches. (Figure 2: P1 and N2). It is rec-
ommended to connect 100nF at V
OUT2 for the LM3502-35V
and LM3502-44 versions if V
OUT2 is not used.
V
OUT1 (Bump D1): Source connection of the internal PMOS
FET switch (Figure 2: P1) and OVP sensing node. The
output capacitor must be connected as close to the device
as possible, between the V
OUT1 pin and ground plane. Also
connect the Schottky diode as close as possible to the
V
OUT1 pin to minimize trace resistance and EMI radiation.
Sw (Bump D2): Drain connection of the internal power
NMOS FET switch. (Figure 2: N1) Minimize the metal trace
length and maximize the metal trace width connected to this
pin to reduce EMI radiation and trace resistance.
PGND (Bump D3): Power ground pin. Connect directly to
the ground plane.
AGND (Bump C3): Analog ground pin. Connect the analog
ground pin directly to the PGND pin.
V
IN (Bump B3): Supply or input voltage connection pin. The
C
IN capacitor should be as close to the device as possible,
between the V
IN pin and ground plane.
En2 (Bump A3): Enable pin for the internal NMOS FET
switch (Figure 2: N2) during device operation. When V
En2 is
www.national.com
2


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