10

FN6162.2

October 10, 2007

GROUND CONNECTIONS

For the best isolation and crosstalk rejection, the GND pin

and NIC pins must connect to the GND plane.

CONTROL SIGNALS

S0, S1, ENABLE, HIZ - These pins are TTL/CMOS

compatible control inputs. The S0 pin selects which one of

the inputs connect to the output. The ENABLE, HIZ pins are

used to disable the part to save power and three-state the

output amplifiers, respectively. For control signal rise and fall

times less than 10ns the use of termination resistors close to

the part will minimize transients coupled to the output.

POWER-UP CONSIDERATIONS

The ESD protection circuits use internal diodes from all pins

the V+ and V- supplies. In addition, a dV/dT- triggered clamp

is connected between the V+ and V- pins, as shown in the

Equivalent Circuits 1 through 4 section of the “Pin

Descriptions” on page 8. The dV/dT triggered clamp

imposes a maximum supply turn-on slew rate of 1V/µs.

Damaging currents can flow for power supply rates-of-rise in

excess of 1V/µs, such as during hot plugging. Under these

conditions, additional methods should be employed to

ensure the rate of rise is not exceeded.

Consideration must be given to the order in which power is

applied to the V+ and V- pins, as well as analog and logic

input pins. Schottky diodes (Motorola MBR0550T or

equivalent) connected from V+ to ground and V- to ground

(Figure 26) will shunt damaging currents away from the

internal V+ and V- ESD diodes in the event that the V+

supply is applied to the device before the V- supply.

If positive voltages are applied to the logic or analog video

input pins before V+ is applied, current will flow through the

internal ESD diodes to the V+ pin. The presence of large

decoupling capacitors and the loading effect of other circuits

connected to V+, can result in damaging currents through

the ESD diodes and other active circuits within the device.

Therefore, adequate current limiting on the digital and

analog inputs is needed to prevent damage during the time

the voltages on these inputs are more positive than V+.

HIZ STATE

An internal pull-down resistor connected to the HIZ pin

ensures the device will be active with no connection to the

HIZ pin. The HIZ state is established within approximately

30ns (Figure 18) by placing a logic high (> 2V) on the HIZ

pin. If the HIZ state is selected, the output is a high

impedance 1.4M

Ω. Use this state to control the logic when

more than one mux shares a common output.

In the HIZ state the output is three-stated, and maintains its

high Z even in the presence of high slew rates. The supply

current during this state is basically the same as the active

state.

ENABLE AND POWER DOWN STATES

The enable pin is active low. An internal pull-down resistor

ensures the device will be active with no connection to the

ENABLE pin. The Power Down state is established when a

logic high (>2V) is placed on the ENABLE pin. In the Power

Down state, the output has no leakage but has a large

capacitance (on the order of 15pF), and is capable of being

back-driven. Under this condition, large incoming slew rates

can cause fault currents of tens of mA. Do not use this

state as a high Z state for applications driving more than

one mux on a common output.

LIMITING THE OUTPUT CURRENT

No output short circuit current limit exists on this part. All

applications need to limit the output current to less than

50mA. Adequate thermal heat sinking of the parts is also

required.

V+

V+

V-

V-

V+

V-

V+

V-

LOGIC

CONTROL

GND

IN0

IN1

S0

OUT

EXTERNAL

CIRCUITS

SCHOTTKY

PROTECTION

V+

V-

POWER

GND

SIGNAL

LOGIC

V+ SUPPLY

V- SUPPLY

DE-COUPLING

CAPS

FIGURE 26. SCHOTTKY PROTECTION CIRCUIT

ISL59440