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L6997DTR Scheda tecnica(PDF) 4 Page - STMicroelectronics |
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L6997DTR Scheda tecnica(HTML) 4 Page - STMicroelectronics |
4 / 23 page L6997 4/23 ON TIME Ton On time duration VREF=VSENSE OSC=125mV 720 800 880 ns VREF=VSENSE OSC=250mV 370 420 470 ns VREF=VSENSE OSC=500mV 210 240 270 ns OFF TIME TOFFMIN Minimum off time 600 ns KOSC/TOFFMIN OSC=250mV 0.3 0.33 VOLTAGE REFERENCE VREF Voltage Accuracy 0 µA < IREF < 100µA 0.594 0.6 0.606 V PWM COMPARATOR Input voltage offset -2 +2 mV IFB Input Bias Current 20 nA INTEGRATOR INT Over Voltage Clamp VSENSE = VCC 0.62 0.75 0.88 V INT Under Voltage Clamp VSENSE = GND 0.45 0.55 0.65 V Integrator Input Offset Voltage VSENSE-VREF -4 -4 mV IVSENSE Input Bias Current 20 nA GATE DRIVERS High side rise time VDR=3.3V; C=7nF HGATE - PHASE from 1 to 3V 50 90 ns High side fall time 50 100 ns Low side rise time VDR=3.3V; C=14nF LGATE from 1 to 3V 50 90 ns Low side fall time 50 90 ns PGOOD UVP/OVP PROTECTIONS OVP Over voltage threshold with respect to VREF 118 121 124 % UVP Under voltage threshold 67 70 73 % PGOOD Upper threshold (VSENSE-VREF) VSENSE rising 110 112 116 % PGOOD Lower threshold (VSENSE-VREF) VSENSE falling 85 88 91 % VPGOOD ISink=2mA 0.2 0.4 V ELECTRICAL CHARACTERISTICS (continued) (VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit |
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