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L6995DTR Scheda tecnica(PDF) 4 Page - STMicroelectronics |
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L6995DTR Scheda tecnica(HTML) 4 Page - STMicroelectronics |
4 / 25 page L6995 4/25 VREF=VSENSE OSC=500mV 380 430 480 ns VREF=VSENSE OSC=1V 220 250 280 ns VREF=VSENSE OSC=2V 120 150 180 ns OFF TIME TOFFMIN Minimum off time 580 ns KOSC/TOFFMIN OSC=250mV 0.4 0.45 VOLTAGE REFERENCE VREF Voltage Accuracy 0 µA < IREF < 100µA 0.891 0.9 0.909 V PWM COMPARATOR Input voltage offset -2 +2 mV IFB Input Bias Current 0.1 µA CURRENT LIMIT AND ZERO CURRENT COMPARATOR ILIM input bias current ILIM to GND = 120KΩ 5 µA KC Current Limit factor RILIM=120 KΩ 0.85 1 1.15 µA PHASE- GND Zero Crossing Comparator offset -2 2 mV GATE DRIVERS High side rise time VDR=5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 70 ns High side fall time VDR=5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 70 ns Low side rise time VDR=5V; C=14nF LGATE from 2 to 4.5V 50 70 ns Low side fall time VDR=5V; C=14nF LGATE from 2 to 4.5V 50 70 ns PGOOD UVP/OVP PROTECTIONS OVP Over voltage trip with respect to VREF 112 115 118 % UVP Under voltage trip 66 69 72 % PGOOD Upper threshold (VSENSE/VREF) VSENSE rising 107 110 113 % PGOOD Lower threshold (VSENSE/VREF) VSENSE falling 86 89 92 % VPGOOD ISOURCE=2mA 0.14 0.2 V INTEGRATOR INT Over Voltage Clamp VSENSE = VCC 1.04 1.07 1.1 V INT Under Voltage Clamp VSENSE = GND 0.82 0.84 0.86 V VSENSE- VREF Integrator Input Offset Voltage -5 5 mV IVSENSE Input Bias Current 0.1 µA ELECTRICAL CHARACTERISTICS (continued) (VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit |
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