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ISL5216KI-1Z Scheda tecnica(PDF) 7 Page - Intersil Corporation |
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ISL5216KI-1Z Scheda tecnica(HTML) 7 Page - Intersil Corporation |
7 / 65 page 7 FN6013.3 July 13, 2007 Input Select/Format Block Each front end block and the level detector block contains an input select/format block. A functional block diagram is provided in the above figure. The input source can be any of the four parallel input busses (see Microprocessor Interface Section Table 1, IWA *000h) or a test register loaded via the processor bus (see Microprocessor Interface Section, GWA register F807h). The input to the part can operate in a gated or interpolated mode. Each input data bus has an input enable (ENIx,x = A, B, C or D). In the gated mode, one input sample is processed per clock that the ENIx signal is asserted (low). Processing is disabled when ENIx is high. The ENIx signal is pipelined through the part to minimize delay (latency). In the interpolated mode, the input is zeroed when the ENIx signal is high, but processing inside the part continues. This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. On reset, the part is set to gated mode and the input enables are disabled. The inputs are enabled by the first global SYNCI signal or SYNCIx signal, where X = 0, 1, 2 or 3. The input section can select one channel from a multiplexed data stream of up to eight channels. The input enable is delayed by zero to seven clock cycles to enable a selection register. The register following the selection register is enabled by the non-delayed input enable to realign the processing of the channels. The one-clock-wide input enable must align with the data for the first channel. The desired channel is then selected by programming the delay. A delay of zero selects the first channel, a delay of one selects the second, etc. The parallel input busses are 17 bits wide allowing for up to 16 bits of fixed-point data or 14 bits of mantissa with three bits of exponent for floating-point data. The input format may be twos complement or offset binary format in either fixed or floating A(15:-1) ENIA B(15:-1) ENIB C(15:-1) ENIC D(15:-1) ENID NOTE: ENI* SIGNALS ARE ACTIVE HIGH (INVERTED AT THE I/O PAD) TESTENBIT TESTENSTRB EXTERNAL DATA INPUT SELECT (IWA *000 - 14:13 or GWA F804 - 14:13) μP TEST REGISTER (GWA F807 - 15:0) (IWA *000 - 11 (GWA F808) or GWA F804 - 11) TEST ENI SELECT (IWA *000 - 12 EXTERNAL/TEST SELECT (IWA *000 - 15 or GWA F804 - 15) or GWA F804 - 12) 15:0 15:0 TESTEN ENI 15:0 EN OFFSET BINARY OR TWO’s COMPLEMENT (IWA *000 - 10 or GWA F804 - 10) FORMAT FLOATING POINT TO FIXED POINT 11/3, 12/3, 13/3 14/2, 14/3, 15/2, 16/1 (IWA *000 or GWA F804 - 17:16, 8:7) R E G PROGRAMMABLE DELAY DE-MULTIPLEX CONTROL (0-7) (IWA *000 - 6:4 or GWA F8O4 - 6:4) 15:0 FIXED POINT OR FLOATING POINT (IWA *000 - 9 or GWA F804 - 9) DATA TO NCO/MIXER INTERPOLATED/GATED MODE (IWA *000 - 3 or GWA F804 - 3) INPUT ENABLE HOLD OFF (ENABLED BY SYNCI) (GWA F802 - 30) DATA SAMPLE ENABLE CARRIER OFFSET FREQUENCY (COF) COF SYNC ENABLE COF RESAMPLER OFFSET FREQUENCY (SOF) SOF SYNC ENABLE SOF ENABLE PN (IWA *000 - 0) PN COF TO CARRIER NCO/MIXER COF SYNC TO CARRIER NCO/MIXER SOF TO RESAMPLER NCO SOF SYNC TO RESAMPLER NCO PN TO CARRIER NCO/MIXER (1WA *000 - 2) (IWA *000 - 1) OR LEVEL DETECTOR ISL5216 |
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