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ISL5216KI Scheda tecnica(PDF) 11 Page - Intersil Corporation |
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ISL5216KI Scheda tecnica(HTML) 11 Page - Intersil Corporation |
11 / 65 page 11 FN6013.3 July 13, 2007 ISL5216 Complex Input Mode In this mode, complex (I/Q) data can be input using two clock cycles with I input first and Q input second. The ENIx signal indicates the clock cycle when I is valid. The Q data is taken on either the next input clock or two clocks after I, as determined by IWA *000H bit 23. The complex multiply is done in two clock cycles: I * COS and I * SIN on the first clock and Q * (-SIN) and Q * COS on the second clock cycle. The first integrator of the CIC is enabled on both clock cycles to add the two products. The rest of the stages are enabled only on the first cycle. In complex input mode, the input level detector uses only I samples for its magnitude computation. The CIC decimation counter is programmed for two times the number of complex input samples. The exponent input must be the same for I and Q for the floating point modes. See IWA *000h for details on controlling the complex input mode. NCO/Mixer After the input select/format section, the samples are multiplied by quadrature sine wave samples from the carrier NCO. The NCO has a 32-bit frequency control, providing sub-hertz resolution at the maximum clock rate. The quadrature sinusoids have exceptional purity. The purity of the NCO should not be the determining factor for the receiver dynamic range performance. The phase quantization to the sine/cosine generator is 24 bits and the amplitude quantization is 19 bits. The carrier NCO center frequency is loaded via the μP bus. The center frequency control is double buffered - the input is loaded into a center frequency holding register via the μP interface. The data is then transferred from the holding register to the active register by a write to a address IWA *006h or by a SYNCI signal, if loading via SYNCI is enabled. To synchronize multiple channels, the carrier NCO phase accumulator feedback can be zeroed on loading to restart all of the NCOs at the same phase. A serial offset frequency input is also available for each channel through the D(15:0) parallel data input bus (if that bus is not needed for data input). This is legacy support for HSP50210 type tracking signals. See IWA=*000 and *004 for carrier offset frequency parameters. After the mixers, a PN (pseudo noise) signal can be added to the data. This feature is provided for test and to digitally reduce the input sensitivity and adjust the receiver range (sensitivity). The effect is the same as increasing the noise figure of the receiver, reducing its sensitivity and overall dynamic range. For testing, the PN generator provides a wideband signal which may be used to verify the frequency response of a filter. The one bit PN data is scaled by a 16-bit programmable scale factor. The overall range for the PN is 0 to 1/4 full scale (see IWA = *001h). A gain of 0 disables the PN input. The PN value is formed as: where S is the sign extension of the 16 bit PN gain register value (IWA = *001H) times the PN chip value and the 16 X’s refer to the PN gain register times the PN chip value. The minimum, non-zero, PN value is 2-18 of full scale (-108dBFS) on each axis (-105dBFS total). For an input noise level of -75dBFS, this allows the SNR to be decreased in steps of 1/8dB or less. The I and Q PN codes are offset in time to decorrelate them. The PN code is selected and enabled in the test control register (F800h). The PN is added to the signal after the mix with the three sign bits aligned with the most significant three bits of the signal, so the maximum level is - 12dBFS and the minimum, non-zero level is -108dBFS. The PN code can be 215-1, 223-1 or 215-1 * 223-1. CIC Filter Next, the signal is filtered by a cascaded integrator/comb (CIC) filter. A CIC filter is an efficient architecture for decimation filtering. The power or magnitude squared frequency response of the CIC filter is given by: where M = Number of delays (1 for the ISL5216) N = Number of stages and R = Decimation factor. The passband frequency response for first (N=1) though fifth (N=5) order CIC filters is plotted in Figure 13. The frequency axis is normalized to fS/R, making fS/R = 1 the CIC output sample rate. Figure 15 shows the frequency response for a 5th order filter but extends the frequency axis to fS/R = 3 (3 times the CIC output sample rate) to show alias rejection for the out of band signals. Figure 14 uses information from Figure 15 to provide the amplitude of the first (strongest) alias as a function of the signal frequency or bandwidth from DC. For example, with a 5th order CIC and fS/R = 0.125 (signal frequency is 1/8 the CIC output rate) Figure 14 shows a first alias level of about -87 dB. Figure 14 is also listed in table form in Table 51 (CIC Passband and Alias Levels). The CIC filter order is programmable from 0 to 5. The CIC may be bypassed by setting the CIC filter order to 0 (IWA = *004h bits 13:9 are all set equal to 1) and the CIC barrel shift (IWA = *004h bits 19:14) to 45 decimal. The CIC output rate must, however, be no more than CLKmax/4 where CLKmax is the maximum clock frequency available on the device (see electrical specifications section). PN VALUE 2-3 2-4 . .... ... .... 2-17 2-18 SSS X X XX XXX XXXX XXX X X Pf () πMf () sin πf R ----- ⎝⎠ ⎛⎞ sin ------------------------ ⎝⎠ ⎜⎟ ⎜⎟ ⎜⎟ ⎛⎞ 2N = |
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