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L6386 Scheda tecnica(PDF) 4 Page - STMicroelectronics |
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L6386 Scheda tecnica(HTML) 4 Page - STMicroelectronics |
4 / 10 page HIN LIN SD HOUT LOUT VREF VCIN DIAG Note: SD active condition is latched until next negative IN edge. D97IN522A Figure 1. Timing Waveforms DC OPERATION (continued) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit Sense Comparator Vio Input Offset Voltage -10 10 mV Iio 6 Input Bias Current Vcin ≥ 0.5 0.2 µA Vol 2 Open Drain Low Level Output Voltage, Iod = -2.5mA 0.8 V Vref Comparator Reference voltage 0.460 0.5 0.540 V For both high and low side buffers @25 °C Tamb 0 1 2 3 4 5 C (nF) 0 50 100 150 200 250 time (nsec) Tr D99IN1054 Tf Figure 2. Typical Rise and Fall Times vs. Load Capacitance 0 2 4 6 8 1012 1416 VS(V) 10 102 103 104 Iq ( µA) D99IN1057 Figure 3. Quiescent Current vs. Supply Voltage L6386 4/10 |
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