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LM4930 Scheda tecnica(PDF) 5 Page - National Semiconductor (TI) |
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LM4930 Scheda tecnica(HTML) 5 Page - National Semiconductor (TI) |
5 / 35 page System Control Registers The LM4930 is controlled with a two-wire serial interface. This interface is used to configure the operating mode, digi- tal interfaces, and delta-sigma modulators. The LM4930 is controlled by writing information into a series of write-only registers, each with its own unique 7 bit address. The follow- ing registers are programmable: BASIC CONFIG REGISTER This register is used to configure the I 2S and PCM interfaces as well as the 48kHz DAC module. The 7 bit address for the BASICCONFIG register is XX10000. (X=0if ADDR is set to logic 0) (X=1if ADDR is set to logic 1) BASIC CONFIGURATION (XX1000). (Set = logic 1, Clear = logic 0) BIT 15 14 13 12 11 10 987654321 0 RESET 0 0 0000000000000 0 Address Register Description 3:0 MODE The LM4930 can be placed in one of several modes that dictate the basic operation. When a new mode is selected the LM4930 will change operation silently and will re-configure the power management profile automatically. The modes are described as follows: (Note 14) Mode Mono Speaker Amplifier Source Headphone Left Source Headphone Right Source Comment 0000 None None None Powerdown mode 0001 None None None Standby mode 0010 Voice None None Mono speaker mode 0011 None Voice Voice Headphone call mode 0100 Voice Voice Voice Conference call mode 0101 Audio (L+R) None None L+R mixed to mono speaker 0110 None Audio (Left) Audio (Right) Headphone stereo audio 0111 Audio (L+R) Audio (Left) Audio (Right) L+R mixed to mono speaker + stereo headphone audio 1000 Audio (Left) Voice Voice Mixed Mode 1001 Voice + Audio (Left) Voice Voice Mixed mode 1010 Voice Audio (Left) Audio (Left) Mixed Mode 4 SOFT_RESET Resets the LM4930, excluding the control registers 5 PCM_LONG If set the PCM interface uses a long frame sync. (Note 12) 6 PCM_COMPANDED If set the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. (Note 12) 7 PCM_LAW If set, the companded G711 data is set to be A-law, else µ-law is assumed (Note 12) 8:9 PCM_SYNC_MODE Sets 1 (00h), 2 (01h) or 4(10h) 16 bit frames per sync. The PCM_SDO pin is tri-stated during the latter frames. (Note 12) 10 PCM_ALWAYS_ON This bit should be set if another codec is using the PCM bus. When set, the LM4930 will drive the clock and sync signals in all modes except Powerdown (Note 12) 11 I2S_M/S I2S master or slave select. If set then I2S = master. Cleared = slave 12 I2S_RES I2S resolution select. If set then 32 bits per frame. If cleared then 16 bits per frame 13 RSVD RESERVED (Note 13) 14 RSVD RESERVED (Note 13) 15 RSVD RESERVED (Note 13) www.national.com 5 |
Codice articolo simile - LM4930_04 |
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Descrizione simile - LM4930_04 |
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