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SL2309ZI-1H Scheda tecnica(PDF) 3 Page - SpectraLinear Inc |
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SL2309ZI-1H Scheda tecnica(HTML) 3 Page - SpectraLinear Inc |
3 / 12 page Rev 1.1, May 29, 2007 Page 3 of 12 SL2309 General Description The SL2309 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and Output Frequency Range The input and output frequency range is the same. But, it depends on the drive and CL levels as given in the below Table 1. Drive CL(pF) Min(MHz) Max(MHz) HIGH 15 10 140 HIGH 30 10 100 LOW 15 10 100 LOW 30 10 66 Table 1. Input/Output Frequency Range If the input clock is DC (GND to VDD) or floating, this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A-max supply current. In PLL by-pass mode (S2=1 and S1=0), the detection circuit is disabled and input frequency range is 10 to 100MHz for standard (-1) drive and 10 to 140MHz for high (-1H) drive. SpreadThru ™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL2309 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Select Input Control The SL2309 provides two (2) input select control pins called S1 (Pin-9) and S2 (Pin-8). This feature enables users to select various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k weak pull-up resistors to VDD. PLL Bypass Mode If the S1 and S2 pins are logic Low(0) and High(1) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks bank A, bank B and CLKOUT clocks are driven by directly from the reference input clock. In this operation mode SL2309 works like a non-ZDB fanout buffer. In this operation mode the input power-down detection circuit is disabled and outputs follow the input clock from DC to rated frequencies based on drive levels and load specifications. High and Low-Drive Product Options The SL2309 is offered with High Drive “-1H” and Standard Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI. Refer to the switching electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve the output-to-output skew and input-to-output specifications given in the switching electrical tables. However, Zero Delay between input and outputs can be adjusted by changing the loading at CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL2309 is designed to operate at VDD=3.3V (+/- 10%). An internal on-chip voltage regulator is used to provide PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Refer to SL23EP09 for 3.3V to 2.5V and SL23EPL09 for 1.8V power supply operations. |
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