Motore di ricerca datesheet componenti elettronici |
|
HCF401XXBC1 Scheda tecnica(PDF) 4 Page - STMicroelectronics |
|
HCF401XXBC1 Scheda tecnica(HTML) 4 Page - STMicroelectronics |
4 / 13 page LOGIC DIAGRAMS (continued) 40102B TRUTH TABLE Control Inputs CLR APE SPE CI / CE Preset Mode Action 1 1 1 1 Inhibit Counter 1 1 1 0 Count Down 11 0 X Synchronous Preset on Next Positive Clock Transition 1 0 X X Preset Asynchrounously 0X X X Asynchronous Clear to Maximum Count Timing Diagram for 40102B and 40103B Notes : 1. 0 = Low level 1 = High level X = Don’t care 2. Clock connected to clock input. 3. Synchronous operation : changes occur on negative-to-positive clock transitions.. JAM inputs : HCC/HCF010B ; MSD = J7, J6, J5, J4 (J7 is MSB) LSD = J3, J2, J1, J0 (J3 is MSB) HCC/HCF40103B Binary ; MSB = J7, LSB = J0 HCC/HCF40102B/40103B 4/13 |
Codice articolo simile - HCF401XXBC1 |
|
Descrizione simile - HCF401XXBC1 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |