Motore di ricerca datesheet componenti elettronici |
|
CD74ACT109ME4 Scheda tecnica(PDF) 1 Page - Texas Instruments |
|
|
CD74ACT109ME4 Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 11 page CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 description/ordering information The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74ACT109E CD74ACT109E 55 °Cto125°C SOIC M Tube CD74ACT109M ACT109M –55 °C to 125°C SOIC – M Tape and reel CD74ACT109M96 ACT109M CDIP – F Tube CD54ACT109F3A CD54ACT109F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H L LX X X H† H† H H ↑ LL L H H H ↑ H L Toggle H H ↑ LH Q0 Q0 H H ↑ HH H L H H L X X Q0 Q0 ‡ Unpredictable and unstable condition if both PRE and CLR go high simultaneously after both being low at the same time CD54ACT109 ...F PACKAGE CD74ACT109 ...E OR M PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q Copyright 2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. |
Codice articolo simile - CD74ACT109ME4 |
|
Descrizione simile - CD74ACT109ME4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |