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MC34701EW Scheda tecnica(PDF) 31 Page - Freescale Semiconductor, Inc |
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MC34701EW Scheda tecnica(HTML) 31 Page - Freescale Semiconductor, Inc |
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31 / 39 page  Analog Integrated Circuit Device Data Freescale Semiconductor 31 34701 TYPICAL APPLICATIONS . Figure 30. Buck Control Loop Bode Plot The frequency of the zero created by the ESR of the output capacitor CO is calculated as: Where CO is the value of the buck regulator output capacitor, and ESR is the equivalent series resistance of the output capacitor. The frequency of the compensating network pole can be calculated as follows: The well designed and compensated buck regulator should yield at least 45 deg. phase margin Φm of its overall loop as depicted in the Figure 30, page 31. Selecting Buck Regulator Output Voltage The 34701 buck regulator output voltage can be set by selecting the right value of the resistors R1, R2 and R4, and can be determined from the following formula (see Figure 29, page 30 for the component references): Where VRef is the buck regulator reference voltage (VRef = 0.8V typ.) at the INV pin, VO is the selected output voltage, IO is the output load current, RL is the DC resistance of the inductor L. It is apparent that the buck regulator output voltage is affected by the voltage drop caused by the inductor serial resistance and the regulator output current. In those applications which do not require precise output voltage, setting the formula for calculating selected output voltage can be simplified as follows: Linear Regulator Output Voltage The output voltage of the linear regulator (LDO) can be set by a simple resistor divider according to the following formula: Where VRef is the linear regulator reference voltage (VRef = 0.8V typ.) at the LFB pin, VLDO is the LDO selected output voltage, RU is the “upper” resistor of the LDO resistor divider, RL is the “lower” resistor of the LDO resistor divider. Figure 31 describes the 34701 linear regulator circuit with the resistor divider RU, RL setting the output voltage VLDO. Figure 31. 34701Linear Regulator Circuit Φm 0 -20 20 -40 -2 70 -3 60 -180 10 100 10 00 1.0 Frequency [k Hz ] Gain [dB] fLC fz(c) f BW fz(E SR) fp(FF) fp(c) 10000 Pha se [Deg.] f zESR () 1 2 πC OESR -------------------------- = f pc () 1 2 πC2 R1R3 R1 R3 + () ------------------------- ---------------------------------------- = R2 V Ref 1 V O I O R L × + () V Ref – R4 -------------------------------------------------------- V O V Ref – R1 ------------------------- + ----------------------------------------------------------------------------------------- × = R2 V Ref 1 V O V Ref – () R1 R4 + () R1 R4 × ------------------------- × --------------------------------------------------------------- × = V LDO V Ref 1 R U R L ------- + ⎝⎠ ⎛⎞ × = LDRV LDO LFB CS MC34701 2.8 V to 6.0 V Input VIN1 RS RU RL CLDO VLDO LCMP LDO Compensat ion |
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