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FAN50FC3 Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FAN50FC3 Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 21 page © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN50FC3 Rev. 1.0.0 2 of 21 Block Diagram + GND EN VIDSEL VID7 SS Z CSCOMP SW1 PWM1 RAMPADJ RT VCC PWM2 PWM3 SW2 SW3 VOSADJ CSREF CSSUM VID5 VID6 VID4 VID3 VID2 VID1 VID0 FBRTN COMP DELAY ILIMIT PWRGD UVLO SHUT DOWN &BIAS OSCILLATOR RESET EN SET RESET RESET DELAY 2/3 PHASE LOGIC CROWBAR CURR ENT LIMIT CURRENT LIMIT CIRCUIT START UP CONTROL DAC BUFF VID DAC PRECISION REFERENCE BOOT CONTROL DAC - UVP DAC + OVP CSREF CURRENT BALANCE CIRCUIT FB Threshold OD + + - - Figure 1. Block Diagram |
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