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74VHC132T Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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74VHC132T Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 7 page 74VHC132 QUAD 2-INPUT SCHMITT NAND GATE PRELIMINARY DATA June 1999 s HIGH SPEED: tPD = 4.9 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =2 µA (MAX.) at TA =25 oC s TYPICAL HYSTERESIS: Vh =1Vat VCC =4.5V s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 8 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 132 s IMPROVED LATCH-UP IMMUNITY s LOW NOISE: VOLP = 0.8V (Max.) DESCRIPTION The 74VHC132 is an advanced high-speed CMOS QUAD 2-INPUT SCHMITT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. Pin configuration and function are the same as those of the VHC00 but the VHC132 has hysteresis. This together with its schmitt trigger function allows it to be used on line receivers with slow rise/fall input signals. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES : 74VHC132M 74VHC132T M (Micro Package) T (TSSOP Package) ® 1/7 |
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