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SN74ACT2226DWR Scheda tecnica(PDF) 4 Page - Texas Instruments

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Il numero della parte SN74ACT2226DWR
Spiegazioni elettronici  DUAL 64 횞 1, DUAL 256 횞 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES
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Produttore elettronici  TI [Texas Instruments]
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SN74ACT2226DWR Scheda tecnica(HTML) 4 Page - Texas Instruments

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SN74ACT2226, SN74ACT2228
DUAL 64
× 1, DUAL 256 × 1
CLOCKED FIRST-IN, FIRST-OUT MEMORIES
SCAS219C – JUNE 1992 – REVISED OCTOBER 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
1AF/AE
2AF/AE
2
14
O
Almost-full/almost-empty flag. AF/AE is high when the memory is eight locations or less from a full or empty
state. AF/AE is set high after reset.
1D
2D
6
18
I
Data input
GND
7
Ground
1HF
2HF
1
13
O
Half-full flag. HF is high when the number of bits stored in memory is greater than or equal to half the FIFO
depth. HF is set low after reset.
1IR
2IR
5
17
O
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full
and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of
WRTCLK after reset.
1OR
2OR
22
10
O
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is
empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during
reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
1Q
2Q
21
9
O
Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK.
OR for the FIFO is asserted high to indicate ready data.
1RDCLK
2RDCLK
24
12
I
Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is
synchronous with the low-to-high transition of RDCLK.
1RDEN
2RDEN
23
11
I
Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-to-high
transition of RDCLK.
1RESET
2RESET
8
20
I
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK
must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must
be reset after power up.
VCC
19
Supply voltage
1WRTCLK
2WRTCLK
3
15
I
Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous
with the low-to-high transition of WRTCLK.
1WRTEN
2WRTEN
4
16
I
Write enable. When WRTEN and IR are high, data is written to the FIFO on a low-to-high transition of
WRTCLK.


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