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74AC11 Scheda tecnica(PDF) 1 Page - STMicroelectronics |
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74AC11 Scheda tecnica(HTML) 1 Page - STMicroelectronics |
1 / 7 page 74AC11 TRIPLE 3-INPUT AND GATE PRELIMINARY DATA May 1997 s HIGH SPEED: tPD = 4 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s HIGH NOISE IMMUNITY: VNIH =VNIL = 28% VCC (MIN.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =24 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 11 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The AC11 is an advanced high-speed CMOS TRIPLE 3-INPUT AND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. The internal circuit is composed of 4 stages including buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES : 74AC11B 74AC11M M (Micro Package) B (Plastic Package) 1/7 |
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