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CX24501 Scheda tecnica(PDF) 2 Page - Synaptics Incorporated. |
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CX24501 Scheda tecnica(HTML) 2 Page - Synaptics Incorporated. |
2 / 4 page set-top box solutions Satellite For a complete HDTV hardware design, the only additional components required are a tuner, demodulator, double data rate (DDR-2) synchronous dynamic random access memory (SDRAM), and flash memory ICs. This level of integration enables a low-cost system bill of materials and allows the flexibility of supporting different modulation and compression technologies with a low cost, highly featured MPEG solution for dual TV set-top box (STB) applications. CX24501 System Block Diagram The CX24501 IC is integrated into a fully engineered interactive TV STB reference development system that implements third- party interactive middleware/real-time operating system (RTOS) platforms and provides a complete set of STB low-level drivers. The STB development platform hardware is designed with a flexible architecture that supports multiple front end tuner/demodulator daughter boards. A mature and robust hardware abstraction layer is assured by re-use of core driver libraries developed over multiple generations of production MPEG ICs. Support for Nucleus+ and Linux OS is included, with the software architected to allow easy porting to other real-time OS. 16 optional Smart Card Reader Smart Card Reader Buttons/LEDs IR Blaster IR RCU Detect CVBS S/PDIF Audio Out SC1 PCI HDMI HDMITx PCI GPIO SC0 IR OUT IR IN USB0 USB2 USB1 USB2 USB1.1 USB2 M-Card M-Card RJ-11 CVBS YC Y/C YPrPb YPrPb DDR2-SDRAM SDRAM1 TSIN0 TSIN1 TSIN2 CX24501 MPEG Decoder S/PDIF L+R Stereo Modem CX20548 DAA 32 DDR2-SDRAM SDRAM0 64 Flash I/0 Bus MII MII MII RJ-45 10/100 PHY Transport Stream Sources/ Sinks V.92 |
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