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TPA5050RSAT Scheda tecnica(PDF) 4 Page - Texas Instruments |
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TPA5050RSAT Scheda tecnica(HTML) 4 Page - Texas Instruments |
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4 / 21 page  www.ti.com DC CHARACTERISTICS TIMING CHARACTERISTICS (1) (2) SCL SDA tw(H) tw(L) tsu1 th1 SCL SDA th2 t(buf) tsu2 tsu3 StartCondition StopCondition TPA5050 SLOS492B – MAY 2006 – REVISED MAY 2007 T A = 25°C, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD Supply current VDD = 3.3 V, fs = 48 kHz, BCLK = 32 fs 1.5 3 mA IOH High-level output current DATA_OUT = 2.6 V 7 13 mA IOL Low-level output current DATA_OUT = 0.4 V 7 13 mA DATA, LRCLK, BCLK, SCL, SDA, Vi = 5.5V, VDD = 3V 20 IIH High-level input current µ A ADD[2:0], Vi = 3.6V, VDD = 3.6V 5 DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0], Vi = 0V, IIL Low-level input current 1 µA VDD = 3.6V For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 µs tw(L) Pulse duration, SCL low 1.3 µs tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 µs tsu2 Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tsu3 Setup time, SCL to stop condition 0.6 µs (1) VPull-up = VDD (2) A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage. Figure 1. SCL and SDA Timing Figure 2. Start and Stop Conditions Timing 4 Submit Documentation Feedback |
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