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TC9257AFG Scheda tecnica(PDF) 5 Page - Toshiba Semiconductor

Il numero della parte TC9257AFG
Spiegazioni elettronici  PLL for DTS
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Produttore elettronici  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
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TC9256, 57APG/AFG
2006-07-14
5
Functions and Operation
Serial I/O Ports
As the block diagram shows, the functions of the TC9256APG, TC9256AFG, TC9257APG and TC9257AFG are
controlled by setting data in the 48 bits contained in each of the two sets of 24-bit registers. Each bit of data in
these registers is transferred through the serial ports between the controller and the DATA, CLOCK and
PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits.
Since all functions are controlled in units of registers, the explanation here focuses on the 8-bit addresses and
functions of each register.
These registers consist of 24 bits and are selected by an 8-bit address.
A list of the address assignments for each register is given below under Register Assignments.
Register
Address
24-Bit Composition
No. of Bits
Input Register 1
D0H
PLL divisor setting
Reference frequency setting
PLL input and mode setting
Crystal oscillator selection
Total
16
4
2
2
24
Input Register 2
D2H
General-purpose counter control
(Including lock-detection bit control)
I/O port and general-purpose counter switching bits
I/O-5/CLK pin switching bit
(DO2/OT-4 pin switching bit for TC9256APG and
TC9256AFG)
DO pin control
TEST bit
I/O port control
(Also used as general-purpose counter input-selection
bits)
Output data
Total
4
3
1
1
1
5
9
24
Output Register 1
D1H
General-purpose counter numeric data
Not used
Total
22
2
24
Output Register 2
D3H
Lock detection data
I/O port control data
Output data
Input data (undefined during output port selection)
Not used
Total
5
5
4
5
5
24
On the falling edge of the PERIOD signal, the input data is latched in register 1 or register 2 and the function
is performed.
On the ninth falling edge of the CLOCK signal, the output data is latched in parallel in the output registers.
The data are subsequently output serially from the data pin.


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