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TC9327BFG Scheda tecnica(PDF) 7 Page - Toshiba Semiconductor

Il numero della parte TC9327BFG
Spiegazioni elettronici  DTS Microcontroller (DTS-21)
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Produttore elettronici  TOSHIBA [Toshiba Semiconductor]
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TC9327BFG
2005-04-20
7
Pin No.
Symbol
Pin Name
Function and Operation
Remarks
67
HOLD
Hold mode control
input
Input pin for request/release hold mode.
Normally, this pin is used to input radio mode
selection signals or battery detection signals.
Hold mode includes CLOCK STOP mode (stops
crystal oscillation) and WAIT mode (halts CPU).
Setting is implemented with the CKSTP instruction
or the WAIT instruction. When the CKSTP
instruction is executed, request/release of the hold
mode depends on the internal MODE bit. If the
MODE bit is “0” (MODE-0), executing the CKSTP
instruction while the HOLD pin is at low level
stops the generator and the CPU and changes to
memory back-up mode. If the MODE bit is “1”
(MODE-1), executing the CKSTP instruction
enters memory back-up mode regardless of the
level of the HOLD pin. Memory back-up is
released when the
HOLD pin goes high in
MODE-0, or when the
HOLD pin input changes
in MODE-1.
When memory back-up mode is entered by
executing a WAIT instruction, any change in the
HOLD pin input releases the mode.
In memory back-up mode, current consumption is
low (below 10
µA), and all the output pins (e.g.,
display output, output ports) are automatically set
to low level.
68
OT1
Output port
1-bit output port.
Note: This output goes high after reset, and
internal latch data is output as is even when
CLOCK STOP is being executed.
72
VDD
69
GND
Power-supply pins
Pins to which power is applied.
Normally, VDD = 1.8 to 3.6 V is applied.
In back-up mode (when CKSTP instructions are
being executed), voltage can be lowered to 1.0 V.
If voltage falls below 1.55 V while the CPU is
operating, the CPU stops to prevent malfunction
(STOP mode). When the voltage rises above 1.55
V, the CPU restarts.
STOP mode can be detected by checking the
STOP F/F bit. If necessary, execute initialization
or adjust clock by program.
When detecting or preventing CPU malfunctions
using an external circuit, STOP mode can be
invalidated and rendered non-operative by
program. In that case, all four bits of the internal
TEST port should be set to “1”.
If more than 1.8 V is applied when the pin voltage
is 0, the device system is reset and the program
starts from address “0”. (power on reset)
Note: To operate the power on reset, the power
supply should start up in 10 to 100 ms.


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