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74LVCE161284DLG4 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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74LVCE161284DLG4 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 16 page www.ti.com PARAMETER MEASUREMENT INFORMATION Input (see Note D) From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 VCC × 2 V Open GND 500 Ω 500 Ω Output Control Output Waveform 1 S1 at VCC × 2 V (see Note C) Output Waveform 2 S1 at GND (see Note C) VOL VOH tPZL tPZH tPLZ tPHZ 1.4 V 1.4 V VOH 0 V 1.4 V VOL + 0.3 V 1.4 V VOH - 0.3 V 0 V 2.7 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VCC × 2 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Input rise and fall times are 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 µs. E. The outputs are measured one at a time, with one transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. tPHL tPLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B to A) 2.7 V VOH VOL 0 V 1.4 V 50% VCC Input (see Note B) Output 1.4 V 50% VCC HOST LOGIC IN TO HOST LOGIC OUT OR B-TO-A LOAD (TOTEM POLE) tPHL tPLH A-TO-B LOAD OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT VOLTAGE WAVEFORMS MEASURED AT TP1 PROPAGATION DELAY TIMES (A to B) 2.7 V VOH VOL 0 V 1.4 V VOH - 1.4 V Output 1.4 V VOL + 1.4 V tw When Measuring the Cable Side, VCC CABLE × 2 V From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 VCC CABLE × 2 V Open GND 500 Ω 500 Ω tPLH tPHL tPLZ/tPZL tPHZ/tPZH Open VCC CABLE × 2 V VCC CABLE × 2 V GND TEST S1 SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES541 – JANUARY 2004 – REVISED MARCH 2005 Figure 3. Load Circuits and Voltage Waveforms 9 |
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