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TC94A48FG Scheda tecnica(PDF) 6 Page - Toshiba Semiconductor |
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TC94A48FG Scheda tecnica(HTML) 6 Page - Toshiba Semiconductor |
6 / 36 page TC94A48FG 2005-09-28 6 1.1 Timing register setting [AIFA] Note 2: In 48fs frequency setup of BCKi-1 and BCKi-0, LRCKi/BCKi coresponds only an input, and LRCKo / BCKo does not correspond. Bit Default 15-14 * 00 32fs 01 48fs 10 64fs 11 64fs 13-12 * 00 32fs 01 48fs 10 64fs 11 64fs 11 * 0 1 10 * 0 1 9 * 0 1 8 * 0 1 7-6 * 00 LSB justified 01 MSB justified 10 I2S 11 I2S 5-4 * 00 16bit 01 18bit 10 20bit 11 24bit 3-2 * 00 LSB justified 01 MSB justified 10 I2S 11 I2S 1-0 * 00 16bit 01 18bit 10 20bit 11 24bit SDi input bit clock SDo output format SDo output bit clock SDo clock select LRCKi-0/BCKi-0 LRCKi-1/BCKi-1 SDi input format Lch=High (interrupt by rise edge) SDi clock select LRCKi-0/BCKi-0 LRCKi-1/BCKi-1 Lch=Low (interrupt by fall edge) Lch=High (interrupt by rise edge) LRCKi-0 polarity Lch=Low (interrupt by fall edge) Contents BCKi-1 clock frequency BCKi-0 clock frequency LRCKi-1 polarity |
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