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TC74HCT138AP Scheda tecnica(PDF) 1 Page - Toshiba Semiconductor |
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TC74HCT138AP Scheda tecnica(HTML) 1 Page - Toshiba Semiconductor |
1 / 8 page TC74HCT138AP/AF/AFN 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT138AP,TC74HCT138AF,TC74HCT138AFN 3-to-8 Line Decoder The TC74HCT138A is a high speed CMOS 3-to-8 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( 0 Y - 7 Y ) will go low. When enable input G1 is held low or either 2A G or 2B G is held high, decoding function is inhibited and all outputs go high. G1, 2A G , and 2B G inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 17 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 V (max) • Wide interfacing ability: LSTTL, NMOS, CMOS • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL • Pin and function compatible with 74LS138 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74HCT138AP TC74HCT138AF TC74HCT138AFN Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) |
Codice articolo simile - TC74HCT138AP_07 |
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Descrizione simile - TC74HCT138AP_07 |
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