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TLP702F Scheda tecnica(PDF) 1 Page - Toshiba Semiconductor |
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TLP702F Scheda tecnica(HTML) 1 Page - Toshiba Semiconductor |
1 / 2 page TLP702F 2007-10-01 1 Weight:0.26 g (t yp.) TOSHIBA 11-5J101 Unit in mm 4.58±0.25 0.4±0.1 1 2 3 1.27±0.2 6 5 4 11.7±0.3 0.75±0.25 7.62±0.25 11-5J101 TOSHIBA PHOTOCOUPLER GaAℓAs IRED & PHOTO-IC TLP702F Intelligent power module signal isolation Industrial inverters Motor drive The Toshiba TLP702F consists of a GaAℓAs light-emitting diode and an integrated high-gain, high-speed photodetector. The TLP702F is suitable for isolating input control signals to intelligent power modules. This unit is a 6-pin SDIP. The TLP702F is 50% smaller than the 8-PIN DIP and meets the reinforced insulation class requirements of international safety standards. Therefore the mounting area can be reduced in equipment requiring safety standard certification. The detector has a totem pole output stage to provide both source and sink driving.The detector IC has an internal shield that provides a guaranteed common-mode transient immunity of 10 kV/μs. The TLP702F is inverter logic type. For buffer logic type, the TLP706F is in line-up. Absolute Maxmum ratings and electrical characteristics are the same as The TLP702 technical data sheets. Inverter logic type ( totem pole output ) Lead(Pb)-Free Guaranteed performance over temperature : −40~100°C Power supply voltage : 4.5~20 V Input current: IFHL = 5 mA (max.) Switching time ( tpHL / tpLH) : 600 ns (max.) Common-mode transient immunity : ±10 kV/μs (min) Isolation voltage : 5000 Vrms (min) UL Recognized :UL1577, File No.E67349 Option (D4) TÜV Approved : DIN EN60747-5-2 No.R50033433 Maximum Operating Insulation Voltage : 1140VPK Highest Permissible Over Voltage : 8000VPK (Note) : When a EN60747-5-2 approved type is needed, Please designate “Option(D4)” Construction Mechanical Rating Truth Table Input LED Tr1 Tr2 Output H ON OFF ON L L OFF ON OFF H Creepage Distance Clearance Insulation Thickness 8.0 mm (min) 8.0 mm (min) 0.4 mm (min) VCC GND SHIELD 1 3 4 5 6 2 1:ANODE 2:N.C. 3:CATHODE 4:GND 5:Vo 6:Vcc Pin Configuration (Top View) 0.1 μF bypass capacitor must be connected between pins 6 and 4. (Note 4) VCC VO GND ICC IO 6 5 4 SHIELD 3- 1+ IF VF Tr1 Tr2 Schematic |
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