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TLP705 Scheda tecnica(PDF) 1 Page - Toshiba Semiconductor

Il numero della parte TLP705
Spiegazioni elettronici  Plasma Display Panel
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Produttore elettronici  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TLP705 Scheda tecnica(HTML) 1 Page - Toshiba Semiconductor

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TLP705
2007-10-01
1
Unit in mm
Weight:0.26 g (t yp.)
4.58±0.25
9.7±0.3
0.4±0.1
1.27±0.2
1.25±0.25
7.62±0.25
1 2 3
6 5 4
11-5J1
TOSHIBA
11-5J1
TOSHIBA Photocoupler GaAℓAs IRED + Photo IC
TLP705
Plasma Display Panel.
Industrial Inverter
IGBT/Power MOS FET Gate Drive
TLP705 consists of a GaAℓAs light emitting diode and a integrated
photodetector.
This unit is 6-lead SDIP package. TLP705 is 50% smaller than 8pin DIP
and has suited the safety standard reinforced insulation class.
So mounting area in safety standard required equipment can be reduced.
TLP705 is suitable for gate driving circuit of IGBT or power MOS FET.
Especially TLP705 is capable of “direct” gate drive of lower Power IGBTs.
• Peak output current
: ±0.45 A (max)
• Operating frequency
: 250kHz (max)
• Guaranteed performance over temperature : −40 to 100°C
• Supply current
: 3mA (max)
• Power supply voltage
: 10 to 20 V
• Threshold input current
: IFLH = 8 mA (max)
• Switching time (tpLH / tpHL)
: 200 ns (max)
• Common mode transient immunity
:±10 kV/μs(min)
• Isolation voltage
: 5000 Vrms(min)
• UL Recognized
:UL1577, File No.E67349
• Construction Mechanical Rating
7.62-mm pitch
standard type
10.16-mm pitch
TLPXXXF type
Creepage Distance
Clearance
Insulation Thickness
7.0 mm (min)
7.0 mm (min)
0.4 mm (min)
8.0 mm (min)
8.0 mm (min)
0.4 mm (min)
• Option (D4)
TÜV approved
: EN60747-5-2
Certificate No. R50033433
Maximum operating insulation voltage
: 890 Vpk
Highest permissible over voltage
: 8000 Vpk
( Note ) When a EN60747-5-2 approved type is needed,
please designate the “Option(D4)”
Truth Table
Input
LED
Tr1
Tr2
Output
H
ON
ON
OFF
H
L
OFF
OFF
ON
L
A 0.1
μF bypass capacitor must be connected
between pins 6 and 4. (See Note 6.)
1
+
3
VCC
VO
GND
(Tr1)
(Tr2)
ICC
IO
IF
VF
6
5
4
SHIELD
Schematic
1: ANODE
2: NC
3: CATHODE
4: GND
5: VO ( OUTPUT )
6: VCC
1
3
5
6
2
SHIELD
Pin Configuration (Top View)


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