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TC74AC390FN Scheda tecnica(PDF) 1 Page - Toshiba Semiconductor |
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TC74AC390FN Scheda tecnica(HTML) 1 Page - Toshiba Semiconductor |
1 / 10 page TC74AC390P/F/FN 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC390P,TC74AC390F,TC74AC390FN Dual Decade Counter The TC74AC390 is an advanced high speed CMOS DUAL DECADE COUNTER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It consists of two independent 4-bit counters, each composed of a divide-by-two and a divide-by-five counter. The divide-by-two counter is incremented on the negative going transition of clock A ( CKA ). The divided-by-five counter is incremented on the negative going transition of clock B ( CKB ). The counter can be cascaded to form decade, bi-quinary, or various combinations up to a divide-by-100 counter. When the CLEAR input is set high, the Q outputs are set to low independent of the clock inputs. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fmax = 160 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Pin and function compatible with 74HC390 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC390P TC74AC390F TC74AC390FN Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) |
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